Intel Thursday announced details of forthcoming chips for compute, graphics, and artificial intelligence in its first architectural roadmap presentation since 2018.
Intel’s Raja Koduri, the company’s chief architect, told reporters that the spirit of the company’s engineers is high despite a couple weeks of grueling press coverage since Intel announced yet another delay in manufacturing on July 23rd.
“The last few weeks, particularly for us inside, have been pretty hard reading what’s written about us,” Koduri told reporters.
“As engineers inside Intel we are we are more energized, more motivated, more excited about our future than ever,” he said.
Koduri, a longtime industry veteran who has previously worked at Advanced Micro Devices and Apple, is one of the senior executives who remains after a shake up of Intel’s operational structure announced July 27th. That included the departure of Venkata “Murthy” Renduchintala, the high-profile chip engineer who was at one time seen as Intel’s savior.
The purge followed the announcement Intel will experience an additional six-month delay in production of its next-generation transistors measuring seven billions of a meter, or 7 nanometers.
Among details offered Thursday were specs of Tiger Lake, a new system-on-chip that will take over from the previous Lake Field; Willow Cove, a new high-performance CPU micro-architecture; multiple versions of the company’s Xe integrated and discrete graphics processors; and a slew of packaging designs that connect different kinds of chips together in both horizontal and vertical arrangements.
Supporting the new designs is a new kind of transistor that Intel calls the “SuperFin,” a play on the FinFET transistor it debuted a decade ago as the first vertically shaped transistor.
Regarding the repeated process delays, Koduri said Intel is freeing itself to some degree from being tied to when it has new transistors ready. By making more chip designs that are disaggregated into “chiplets,” Intel can go from design to production in only 12 to 15 months versus the 24- to 30-month cycles that traditionally dominate chip manufacture.
“We are way better set up now than we were a couple of years ago,” said Koduri.
One of the deputies charged with increasing Intel’s options is Ramune Nagisetty, who is vice president of product and process integration. Nagisetty explained how the various ways of packaging chips together is allowing Intel to source more pieces of intellectual property from outside the company so that designs for chips don’t have to be as monolithic as they were in past.
“We’ve tested out this disaggregation strategy on lower-volume products, and it’s increasing and becoming more pervasive,” said Nagisetty.
For example, a technology that is just being tested this quarter is hybrid bonding, which is a follow-on to Intel’s Foveros technology for stacking chips vertically one on top of another. It reduces the amount of power needed to make chips communicate across the wires between them.
Intel now has greater flexibility to choose which kinds of manufacturing it uses, said Brijesh Tripathi, Intel’s graphics and software general manager. That includes going outside Intel’s own factories, he said.
“We will figure out what the sourcing options are, whether it’s Intel or external or a combination,” he said. “We will pick the right process at the right time.”
See also: Intel’s 7nm products delayed | Rise of ARMs: How changing Mac’s processor could change the world | Linus Torvalds: I hope Intel’s AVX-512 ‘dies a painful death’ | Ex-Intel engineer: Apple turned away from Intel over Skylake CPU bugs
The product details publicized Thursday emphasize Intel’s ability to mix and match different capabilities in its chips. Tiger Lake, which will integrate four Willow Cove CPUs and a low-power version of Xe graphics, XeLP, will also feature a slew of input-output advances, including Thunderbolt 4, USB 4, and PCIe Gen 4.
The company also teased another hybrid system-on-chip, called Alder Lake, coming sometime in 2021, that will combine a CPU called Golden Cove with a core chip called Gracemont, a combo known as a big+little chip, to balance high-performance with energy efficiency.
Intel still wants to emphasize its manufacturing prowess. It places great emphasis on the ability to manipulate materials to improve the physics of its devices.
The new transistors discussed, SuperFin, will come with multiple benefits including additional gate pitch that allows for higher drive current for greater performance; an improved gate process that boosts carrier mobility; and an enhanced epitaxial layer of crystal structure over the transistor’s source and drain that allows more current to flow.
There is also a novel capacitor design that Intel calls the Super MIM. It has novel materials achievements that Intel claims no other manufacturer can produce, such as a lattice of two different kinds of Hi-K materials measuring only angstroms thick that are spread in levels throughout the silicon structure.
The SuperFin part will be made in Intel’s 10-nanometer process technology and will be used to create Tiger Lake parts that will ship in computers this holiday season, the company said. SuperFin will also show up in a new Xeon server processor out later this year called Sapphire Rapids.
Even if Koduri and team can deliver on diversity and alacrity, Intel faces a different challenge than time to market. Its offerings remain a complex buffet in a field where competitors tend to have a more streamlined portfolios, such as Nvidia’s focus on its Ampere graphics architecture.
The flip side of Intel’s diversity is the need to make clear to customers what products are for what use cases.
“We are definitely making progress on reducing the confusion for our customers, we are not there yet completely,” Koduri told ZDNet. “Part of it is cleaning up our past sins.”
The answer, said Koduri, will be the unified software stack spanning the various chip offerings.
“Even internally, we are settling on this term XPU, it’s very important,” said Koduri, referring to the umbrella acronym Intel uses to summarize a spectrum of different kinds of chips.
“The compute element on which the software will run is made up of multiple heterogenous elements,” he said.
“It’s the software element that brings all these things together.”